This invention relates to the field of integrated circuit (IC) design. Specifically, it relates to a data clock system for reliable high-speed data transfers within a synchronous embedded semiconductor memory system having a micro-cell architecture arranged in a wave-pipe structure.
EDRAMs with wide data bandwidth and wide internal bus width have been proposed to be used as L2 (Level-2) cache to replace pure SRAM cache. Since each DRAM memory cell is formed by a transistor and a capacitor, the size of DRAM cache is significantly smaller than that of SRAM cache. It is beneficial to use eDRAM systems in embedded applications, such as hand-held systems, for reducing size, power consumption and cost.
In order to meet performance requirements, an eDRAM is formed of a plurality of blocks or micro-cells arranged in arrays forming one or more banks. A block is a small DRAM array unit formed by a plurality of word lines (e.g., from 64 to 256) and a plurality of bitline pairs (e.g., from 64 to 256). The size of a block is much smaller (e.g., 16xc3x97 to 256xc3x97) than that of a bank of a conventional stand-alone DRAM. Typically, one block of each eDRAM bank is activated within a clock cycle. In order to facilitate a high data-rate during data transfers it is possible for blocks from different banks to be accessed simultaneously for simultaneous read and write operations. The read and write speed of an eDRAM can be fast due to very light loading of word lines and bitlines.
While the data transferring speed in a high-performance memory is critical, the advantage of high speed is useless without reliable data transferring. Reliability of data is compromised by factors such as noise coupling, data pulse racing, incorrect data latching due to data skew and extra power due to signal glitch. In particular, in order to reduce timing-related problems for improving data reliability during data transferring, it is important to prevent data collision during data read operations regardless of the location in which the data is stored, and to correlate control and address signals properly during their transmission for insuring that the correct data is latched in data registers during each clock cycle.
In a known wave-pipe system for stand-alone DRAM described in xe2x80x9cA Study of Pipeline Architectures for High-Speed Synchronous DRAM""sxe2x80x9d by Hoi-Jun Yoo, IEEE Journal of Solid State Circuits, Vol. 32, October 1997, pages 1597-1603, a self-resetting logic for reducing the pulse width is described. However, it has become common for pulse-widths to be increasingly smaller. Further, reduction of the pulse width adds a risk of additional data reliability problems.
Accordingly, a need exists for a high-speed semiconductor memory system and method for providing reliable high-speed data transfers in which timing-related data reliability problems are reduced. Furthermore, a need exists for a high-speed semiconductor memory system and method in which a data clock system is provided for reducing the possibility of a data collision during a read operation or latching the wrong data during a write operation. Furthermore, a need exists for a method and system for providing a data clock system having an increased timing window for reliable read and write operations without reducing the pulse width of the data clock.
An aspect of the present invention is to provide a high-speed semiconductor memory system and method for providing reliable high-speed data transfers in which timing-related data reliability problems are reduced.
Another aspect of the present invention is to provide a high-speed semiconductor memory system and method in which a data clock system is provided for reducing the possibility of a data collision during a read operation or latching the wrong data during a write operation.
Another aspect of the present invention is to provide a method and system for providing a data clock system having an increased timing window for reliable read and write operations without reducing the pulse width of the data clock.
Accordingly, a data clock system for a semiconductor memory system is provided. The semiconductor memory system includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths, each first data path in operative communication with a second data path. The data clock system includes a first clock path receiving a clock signal during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; and a second clock path receiving the clock signal from the first clock path and propagating the clock signal along therethrough, the second clock path including at least one clock driver. The transfer of data between the one of the plurality of first data paths and the second data path occurs upon receipt of the clock signal by the at least one clock driver. The clock signal is delayed during propagation along the first clock path and the second clock path by approximately the same amount of time regardless if the at least one clock driver is positioned proximate a far end of the second clock path or the at least one clock driver is positioned proximate a near end of the second clock path.
Furthermore, a method for propagating a clock signal in a semiconductor memory system is provided. The semiconductor memory includes a plurality of data banks configured for storing data, the plurality of data banks in operative communication with a plurality of first data paths. The method includes the steps of receiving a clock signal in a first clock path during a data transfer operation for transferring data between one data bank of the plurality of data banks and the second data path via one of the plurality of first data paths; receiving the clock signal in a second clock path; propagating the clock signal along the second clock path via at least one clock driver; and transferring the data between one of the first data paths and the second data path upon receipt of the clock signal by the at least one clock driver. The method further includes the step of delaying the clock signal by a clock delay during propagation of the clock signal along the first clock path and the second clock path until arriving at the associated clock driver. The clock delay is approximately the same when the associated clock driver is positioned proximate a far end of the second clock path and when the associated clock driver is positioned proximate a near end of the second clock path.